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Need help - vhdl synplify

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nge

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How can I specify timing constraint in vhdl code as attributes? I don't want to use constraint file, I want to put them in vhdl code as attributes. I know how to do that for pin assignments. But I have a problem with timing constraints. This is a piece constraints from .ucf file. I am trying to synthesise with Synplify Pro. Any help will be great. Thanks.

NET "clk" TNM_NET = "TNM_CLK";
TIMEGRP "CLK_PAD" = "pads(clk)";
NET "clk" MAXDELAY = 3.0ns;
TIMESPEC TS_CLK_FFS_FFS = PERIOD "TNM_CLK" 20.0ns HIGH 50%;

TIMEGRP "LD_PADS" OFFSET = OUT 14.5ns AFTER "clk";
 

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