Need help understanding pins features of FPGA's for assignment

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Hello all..

I am trying to understand pin assignment for FPGA's. I am currently working on Altera Stratix III - EP3sl70.
Any resources like videos or pdf's or some other tutorials would be very helpful.

Thanks..
 

Take a look here,
**broken link removed**
 

vipinlal said:
Take a look here,
**broken link removed**
Click to expand...

Thanks..!! I was able to do an acceptable pin assignment and soft of played around with the chip planner.. I know that if the I can make short route between pins and the LUT's & LAB's, I can minimize the propagation delay.

I want to understand how I can place the pins such that I get an optimized design.
 

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