need help to correct the code related to that architecture

[Suganya Subramanian]

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Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sorter1 is
    port(a : in std_logic_vector(15 downto 0);
         b : in integer;
         clk : in std_logic;
         c : out std_logic_vector(15 downto 0);
         c1 : out integer);
end sorter1;
architecture behav of sorter1 is
    signal s11,s21,s31,s41,s51,s61 : std_logic_vector(15 downto 0);
    signal s12,s22,s32,s42,s52,s62 : integer;
    signal s2,s3,s4,s5,s6,s7 : std_logic;
    signal vi1 : integer := 1; 
    signal vi2 : integer := 2;
    signal vi3 : integer := 3;
    signal vi4 : integer := 4;
    signal vi5 : integer := 5;
    signal i : integer := 0;
component control_module
   port (i1 : in integer;
         en1 : out std_logic;
         en2 : out std_logic;
         en3 : out std_logic;
         en4 : out std_logic;
         en5 : out std_logic;
         en6 : out std_logic);
 end component;
 begin
  l1 : control_module port map (i1=>b, en1=>s2, en2=>s3,                   en3=>s4, en4=>s5,en5=>s6,en6=>s7);
process (clk,i)
 begin  
   if (clk'event and clk = '1') then
   if (s2='1') then
       s11 <= a; 
        s12 <= b; 
     c <= s11; c1 <= s12; 
 elsif (s3 = '1') then
          s21 <= a;
          s22 <= b; 
      c <= s21; c1 <= s22; 
 elsif ( s4 = '1') then
          s31 <= a;
          s32 <= b; 
       c <= s31; c1 <= s32;
 elsif (s5 = '1') then
          s41 <= a;
          s42 <= b;
       c <= s41; c1 <= s42;
 elsif (s6 = '1') then
          s51 <= a;
          s52 <= b;
       c <= s51; c1 <= s52;
 elsif (s7 = '1') then
          s61 <= a;
          s62 <= b;
        c <= s61; c1 <= s62;
  end if;
  end if;
  end process; 
  end behav;
 
 
 
control module
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity control_module is
port (i1 : in integer;
      en1 : out std_logic;
      en2 : out std_logic;
      en3 : out std_logic;
      en4 : out std_logic;
      en5 : out std_logic;
      en6 : out std_logic);
end control_module;
architecture beh of control_module is
type mvu is array (0 to 5) of integer;
signal s1 : mvu := (1,2,3,4,5,6);
begin
process (i1)
begin
   if (i1 = s1(0)) then
      en1 <= '1'; 
      en2 <= '0';
      en3 <= '0'; 
      en4 <= '0'; 
      en5 <= '0';
      en6 <= '0'; 
   elsif (i1 = s1(1)) then
      en1 <= '0'; 
      en2 <= '1';
      en3 <= '0'; 
      en4 <= '0'; 
      en5 <= '0';
      en6 <= '0';
   elsif (i1 = s1(2)) then
      en1 <= '0'; 
      en2 <= '0';
      en3 <= '1'; 
      en4 <= '0'; 
      en5 <= '0';
      en6 <= '0';
   elsif (i1 = s1(3)) then
      en1 <= '0'; 
      en2 <= '0';
      en3 <= '0'; 
      en4 <= '1'; 
      en5 <= '0';
      en6 <= '0';
   elsif (i1 = s1(4)) then
      en1 <= '0'; 
      en2 <= '0';
      en3 <= '0'; 
      en4 <= '0'; 
      en5 <= '1';
      en6 <= '0'; 
  elsif (i1 = s1(5)) then
      en1 <= '0'; 
      en2 <= '0';
      en3 <= '0'; 
      en4 <= '0'; 
      en5 <= '0';    
      en6 <= '1';    
 else
 end if;
 end process; 
 end beh;

---

 

[TrickyDicky]

Whats the problem?
Your control module produces latches, and the i1 and s1 signals are 32 bits wide - why?

 

[Suganya Subramanian]

help me how to correct that?

 

[TrickyDicky]

first, constrain integers so that they dont use all 8 bits:

example:

signal i : integer range 0 to 7; --will be limited to 3 bits when compiled

As for your latches, in an asynchronous process you need to ensure all signals are assigned in ALL cases. SO you are not allowed the empty else clause at the bottom of the process. en1-6 must all be assigned in there. Alternatively, use a default assignment on the signals - assign en1-6 to somethign before the first if statement, and then override it inside the if.

Finally - why is s1 a signal? shouldnt it be a constant?