Need help on the post layout simulation

postlayout extraction -mentor

I am designing a fully differential amplifier, and found it is useless to take pre-layout simulation on the characteristics such as CMRR, PSRR, off set and so on, because in the schematic the two arms of the amplifier always matched well and the simulation result is always very good. So i want to take a post-layout simulation. I am using cadence virtuso tools.
Could anyone give some instructions on how to take a post layout simulation job, such as LPE,PRE, and so on. Is there any material about this topic?

thanks in advance.

lpe netlist and simulation

For a post layout simulation, you can extract parasitics of your layout through some extractor like STAR RC or pascal...well as you are working with analog design, better to use a 3D extractor like pascal which will give you an accurate picture of the parasitics involved in your design.. The extractor tool needs GDS and your circuit netlist as input along with technology files.. Do an extraction and get a LPE netlist (layout parasitic extracted netlist). Use the LPE netlist as your simulation netlist. Feed it to any simulator -hspice, hsim etc. and check your results. You can check with synopsys site for STAR RC

post layout extraction

Hi walker
you can first simulate with a pre-defined mismatch from devices in schematic. That gives you insight how much the results will be altered if your final silicon has such mismatch effect. You can also run monte carlo simulation to have process variation output. For post layout extraction, if you did match well in your device, i don't see any chances u will get mismatch results, as layout is also an ideal drawing. Of coz, if your drawing is bad, tends to have parasitic RC coupling, your AC performance will be reflected.

Most of time ppl use calibre XRC or Star-RCXT as the tool to do parasitic extraction. You need to get ITF files from foundries or some of their database to have layer representation, then you plug into calibre or star-rcxt to run layout extraction, then you got the netlist with RC parasitics, plug it back to simulator, you got the results. Be careful somtimes post layout netlist may screw up your simulation due to some dangling nets which are not being initialized.

post layout simulation cadence star

The problem of the fab out device is that under low voltage (2.5V) the PSRR decrease obviously, when Vdd=5V, PSRR=70~80dB, which is normal, but when vdd=2.5V PSRR=50~60dB. In another word, the mismatch is not obvious when supply voltage is enough, but when voltage is not enough, the mismatch appear. But the pre-layout simulation can not show how this mismatch take place when vdd=2.5V, so i decide to carry out a post layout simulation to check what happened when supply voltage was decreased to 2.5V.

Now our company only has DRACULA files for this process, so maybe i will first try to use DRACULA...

Usually if someone is laying out a diffamp and they know what they are doing, the differential transistors and the loads are well matched. I think the most important thing you are missing is transistor mismatch due to process/photo variation. You will not get this from extracting parasitics from a layout. Try and look up what the mismatch of the transistors are for your technology and simulate them at 2.5V

Hi walker

When u did simulation at VDD=2.5V, how's your margin for VDS compared to VDS(sat), will there be chances some of your transistors are touching linear/saturation region that once there's a mis-match in process, in real silicon, some transistors are not saturated. I think you should work out for a plot for PSRR vs VDD from 2.0V to 5.5V to check out for the corner it happens, then go check the simulation for corner case. U can do a simple input offset measurement to check out the mis-match from input pairs to extrapolate if this can be happened to other transistors. Connect both inputs to Vcm and measure the VOUT to check the offset, you should know how mis-match varies

Added after 10 minutes:

Hi walker,

Something arouses me, why you think the degradation of PSRR comes form mis-match?
I think the mis-match should be a fairly constant value which does not depend on VDD. So, your guess from mis-match may not be correct.
For the change of PSRR, w.r.t VDD, in AC wise, PSRR = VOUT (change) / VDD (change), so it does not depend on absolute VDD. In real case, it does as the circuit performs differently across different VDD, so why your circuit performance changes with different VDD? it must be sth come from your circut that cannot be operable in such low VDD. So Pls do check your circuit if it really can work under such low voltage. i bet you use thick oxide transistors to do your design, since you work at 5V and now you work at 2.5V, which is normally for thin device, so your transistors' VT has already been greater, and thus you need more margin for VDS to be saturated, if your circuit has cascoded stucture, it may happen that your transistors are likely under marginal saturation region. If your circuit works fine, check for your biasing circuit then if it can really work under such low VDD.

Hope this can help you