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need help on the design of decimation filter

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shameem

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hi,
i want to implement a decimation filter on blackfin 533 processor which should decimate the input sequence by 4. i have read two technique to design such filter. According to the first technique, we wait four 4 samples to come to do the filtering process once. In this way we decimate the samples before filtering. The second approach can be to design a polyphase filter.
Now i am confused which technique should i adopt so that my filter take minimum processor cycle.
if anybody have some idea, please helpme.
 

shirzadi

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I recommended this book:
"Multirate Digital Signal Processing"
Ronald E. Crochiere, Lawrence R. Rabiner
 

wwfhm2002

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4:1 is very simple, normal is FIR and 4:1. the FIR filter can be designed as 1+z-1+z-2+z-3, or other coefficent according your input signal frequency spectrum and required SNR.
 

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