Hi,
It looks like you have a 9 layer process without any parasitics. Your physical library (.pdb) may not be complete.
Did you build your pdb from LEF? LEF is very easy to read.
In the LEF, look for the keyword "LAYER M1" ; you should have a LAYER keyword for each of your 9 layers.
After you find LAYER look down a bit for the keyword RESISTANCE ; stop looking when you hit "END M1" .
You should also have a CAPACITANCE entry as well.
If you do not have these parasitics defined, the tool will not be able to estimate wire delay. As such, you will not be doing "physical" synthesis.
That is why these are ERRORS.