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Need help on forward body biasing!!

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jatan1

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Hi fellow members!

i need help on the topic of forward body biasing.

I am currently using the 65nm process with a wp/wn ratio of 240/120 which is 2.

In regards to the body of the pmos and nmos, i normally tie them to VDD and GND respectively. However, coming upon the topic of forward body biasing i am quite confused as to how should i implement the technique? Could anyone help me out? Thanks! :)

My goal is to simulate my circuit in ultra low power which Vdd as low as 0.2V to 0.4V. Would appreciate any form of help.
 

dick_freebird

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I am not a fan of this. Yes, you can lower the "effective VT"
by about 0.6V/V. But you also are forward-biasing the
parasitic BJT base, and even if you don't "quite" get to
elevated DC drain current you are pushing further into
substrate noise amplification.

Now with that low a VDD, maybe you can't light it up
and don't care.

I would suggest using a replica feedback bias scheme
to servo body voltage to "what you want from the FET".
If it's zero VT(1uA) then you put a G=0, S=0, B=amp
output, D w/ 1uA load = amp feedback replica device
in a control loop and hope for chip-wide matching.

But if you don't need that last couple octaves of speed,
you could just design in subthreshold and take what
comes, at much less complexity / risk.
 

jatan1

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I am not a fan of this. Yes, you can lower the "effective VT"
by about 0.6V/V. But you also are forward-biasing the
parasitic BJT base, and even if you don't "quite" get to
elevated DC drain current you are pushing further into
substrate noise amplification.

Now with that low a VDD, maybe you can't light it up
and don't care.

I would suggest using a replica feedback bias scheme
to servo body voltage to "what you want from the FET".
If it's zero VT(1uA) then you put a G=0, S=0, B=amp
output, D w/ 1uA load = amp feedback replica device
in a control loop and hope for chip-wide matching.

But if you don't need that last couple octaves of speed,
you could just design in subthreshold and take what
comes, at much less complexity / risk.

i realize in some circuits, simply apply a "0" to the pmos body and this provides FBB. Dont seem to understand why though.
 

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