jason7361
Newbie level 4
Can anyone help me to clarify the following verilog question?
Question 1:
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end
I think the above verilog code will always display a= 0 all the time, am i correct?
Or will it display a= 0 at current clock cycle, and it will display a = 1 at next clock cycle?
Can anyone explain how this question works in detail?
I am still confused about blocking and nonblocking assignment in Verilog
Question2:
c = foo ? a : b;
For the above conditional statement, I know if foo = true(1), c=a, and foo = false(0) c=b. But what if foo = "x" value, what answer will i get?
Can anyone explain in detail?
Thank you
Question 1:
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end
I think the above verilog code will always display a= 0 all the time, am i correct?
Or will it display a= 0 at current clock cycle, and it will display a = 1 at next clock cycle?
Can anyone explain how this question works in detail?
I am still confused about blocking and nonblocking assignment in Verilog
Question2:
c = foo ? a : b;
For the above conditional statement, I know if foo = true(1), c=a, and foo = false(0) c=b. But what if foo = "x" value, what answer will i get?
Can anyone explain in detail?
Thank you