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need help,,newbie for VHDL...

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friendz101

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I am trying to do my assignment, I got this error in my port map

Code:
Error (10500): VHDL syntax error at FA.vhd(34) near text "port";  expecting "(", or "'", or "."
Error (10500): VHDL syntax error at FA.vhd(38) near text ")";  expecting "<="
this my program...the error is in my port map???
I am newbie in Quartus...help me plz...

Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity DU is port(
        clk,rst                    :    in std_logic;
        dataA,dataB                :    in std_logic_vector(31 downto 0);
        Psel,Qsel,Rsel,Tsel        :     in std_logic_vector(1 downto 0);
        Use1,Wsel                :    in std_logic_vector(2 downto 0);
        ldA,ldB,ldE1,ldE2,ldM1,ldM2,ctrlM1,ctrlM2,ldP,ldQ: in std_logic;
        A_tp,B_tp                :    out std_logic_vector(31 downto 0);
        E1_tp,E2_tp,P,eq,lt     :    out std_logic_vector(7 downto 0);
        M1_tp,M2_tp,Q            :    out std_logic_vector(21 downto 0)                
);
end DU;

architecture DU_arch of DU is
    signal Ain,Bin        :std_logic_vector(31 downto 0);
    signal E1in,E2in    :std_logic_vector(7 downto 0);
    signal M1in,M2in    :std_logic_vector(21 downto 0);
    signal zero1        :std_logic;
    signal Pin            :std_logic_vector(7 downto 0);    
    signal Qin            :std_logic_vector(21 downto 0);
    
    

component RegE1 port(
    d            :    in std_logic_vector(7 downto 0);
    en,clk,rst    :    in std_logic;
    q            :    buffer std_logic_vector(7 downto 0));
end component;

component RegE2 port(
    d            :    in std_logic_vector(7 downto 0);
    en,clk,rst    :    in std_logic;
    q            :    buffer std_logic_vector(7 downto 0));
end component;
    
component RegA port(
    d            :    in std_logic_vector(31 downto 0);
    en,clk,rst    :    in std_logic;
    q            :    buffer std_logic_vector(31 downto 0));
end component;

component RegB port(
    d            :    in std_logic_vector(31 downto 0);
    en,clk,rst    :    in std_logic;
    q            :    buffer std_logic_vector(31 downto 0));
end component;

component RegM1 port(
    d                    :    in std_logic_vector(21 downto 0);
    ldsh,en,w,clk,rst    :    in std_logic;
    q                    :    buffer std_logic_vector(21 downto 0));
end component;

component RegM2 port(
    d                    :    in std_logic_vector(21 downto 0);
    ldsh,en,w,clk,rst    :    in std_logic;
    q                    :    buffer std_logic_vector(21 downto 0));
end component;

begin

zero1 <= '0';
RegA port map( dataA,ldA,clk,rst,Ain);
RegB port map( dataB,ldB,clk,rst,Bin);
RegE1 port map( E1in,ldE1,clk,rst,E1_out);
RegE2 port map( E2in,ldE1,clk,rst,E2_out);
RegM1 port map( M1in,ctrlM1,ldM1,zero1,clk,rst,M1_out); 
RegM2 port map( M2in,ctrlM1,ldM1,zero1,clk,rst,M2_out);
RegP port map( Pin,ldP,clk,rst,P);
RegQ port map( Qin,ldQ,zclk,rst,Q);
part of error
Code:
RegA port map( dataA,ldA,clk,rst,Ain);
RegB port map( dataB,ldB,clk,rst,Bin);
RegE1 port map( E1in,ldE1,clk,rst,E1_out);
RegE2 port map( E2in,ldE1,clk,rst,E2_out);
RegM1 port map( M1in,ctrlM1,ldM1,zero1,clk,rst,M1_out); 
RegM2 port map( M2in,ctrlM1,ldM1,zero1,clk,rst,M2_out);
RegP port map( Pin,ldP,clk,rst,P);
RegQ port map( Qin,ldQ,zclk,rst,Q);
 

kalyansrinivas

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port map error...someone help me plz!!

you should add both instantiation name and module name

instead of
RegA port map( dataA,ldA,clk,rst,Ain);

write

inst_RegA : RegA port map( dataA,ldA,clk,rst,Ain);

regards
M Kalyansrinivas
 

friendz101

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Re: port map error...someone help me plz!!

thanks for the reply..and it's work
:):)

but I got another problem.

I am got this error for my program,

Code:
Error (10454): VHDL syntax error at FA.vhd(217): right bound of range must be a constant
Code:
entity RegM1 is
port (	ldsh,w,clk,en,rst	: 	in std_logic;
		d			:	in std_logic_vector(21 downto 0);
		q			:	buffer std_logic_vector(21 downto 0));
end RegM1;


architecture archRegM1 of RegM1 is 
signal X : integer range 0 to 255; 

begin
	process(clk,rst)begin
		if rst = '1' then q	<=(others =>'0');
		elsif(clk'event and clk = '1')then
				if en = '1' then 
						if ldsh = '1' then q <= d;
						else
						q(21) <=w;
											
						X <= CONV_INTEGER(d);
						for i in 0 to X  loop
							q(i)<=q(i+1);
						end loop;
						end if ;
				end if;
		end if;					
end process;
end archRegM1;
how I fix this??
I want to shift this register depend on the result of the other process??
how I should do... help me!!!
 

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