need help in VHDL FIR filter..!

[scrawler232]

Hi

I have attached my VHDL fir file code, please help me in identifying the mistake

 

[TrickyDicky]

you are missing a signals from the datapath process sensitivity list.

As well as pres_state, s2 and s3, you also need to include: reg, sel, temp_reg.

Also, ALL signals need an output in EVERY state, or latches are created. I can see that "oe" "t_reg" only get set in certain states.

Added after 28 seconds:

To avoid the problems above, change from the 2 process state machine to a 1 process state machine.