need help in vhdl coding in the following code

[Swapnika.J]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity final is
port (dataout :in std_logic_vector(31 downto 0);
addrout : in std_logic_vector (5 downto 0);
out1 : out std_logic_vector(31 downto 0);
matchhit :in std_logic );
end final;

architecture Behavioral of final is
begin

process(dataout,addrout,matchhit)
begin
case matchhit is
when '0' => out1 <= dataout(31 downto 0);
when others => out1 <= addrout(5 downto 0);

end case;
end process;

Error:length of expected is 32;length of actual is 6

end Behavioral;

 

[alexan_e]

in this line when others => out1 <= addrout(5 downto 0); you assign a 6bit vector to a 32bit vector

you can assign this 6bit result to specific bits, for example when others => out1(5 downto 0) <= addrout(5 downto 0);
you can also assign 0s in the rest of the bits when others => out1(31 downto 6) <=(others => '0');

Alex

 

[engrMunna]

you are assigning addrout (a 6 bit vector) to out1 (a 32 bit vector)... u can do like this
when others => out1(5 downto 0) <= addrout(5 downto 0); out1(31 downto 6) <= (others => '0');