need help in Parallel to Serial VHDL program

[Sarikas]

Hello,

I have a doubt about the following VHDL code to convert from parallel to serial. This code was already discussed in the forum :

https://www.edaboard.com/threads/127794/

I am rewritting the code here for clarity:
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity PAR2SER is
port (DIN : in std_logic_vector (7 downto 0);
MODE : in std_logic_vector (1 downto 0);
CLK, RESET : in std_logic;
SDOUT : out std_logic);
end PAR2SER;
architecture BEHAVIOR of PAR2SER is
signal IDATA : std_logic_vector(7 downto 0);
begin
process (CLK, RESET)
begin
if RESET = '1' then
SDOUT <= '0';
IDATA <= "00000000";
elsif CLK'event and CLK = '1' then
case MODE is
when "00" =>
null;
when "01" =>
IDATA <= DIN;
when "10" =>
SDOUT <= IDATA(7);
for mloop in 6 downto 0 loop
IDATA(mloop+1) <= IDATA(mloop);
end loop;
when others =>
null;
end case;
end if;
end process;
end BEHAVIOR;
------------------------------------------------------------
I still doubt, why the mode pin is used here ??? how is the for loop working as a shift register??? .....

I am stuck with this coding, somebody please help me out....!!!!

 

[TrickyDicky]

the mode seems to work as an enable. it either enables the output or the shift register (but I dont understand why).

the for loop works as a shift register because it assigns the next value in the array with the previous.

 

[achandra]

The mode pin functionality looks like a data valid signal. The user who is driving this module need not necessarily continuously drive the DIN. So whenever he drives a valid input on DIN he will drive a value of '01' of DIN.

From here things are getting a bit vague. If it were me, i would have automatically transitioned the code from Mode 01 to mode 10 even if it's in the other clock cycle.. I guess the design was partitioned to do the functionality in two clock cycles to meet some timing constraints or so.