Hello
I have a question about the following VHDL code to convert from parallel to serial:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PAR2SER is
Port ( DIN : in STD_LOGIC;
MODE : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
SDOUT : out STD_LOGIC);
end PAR2SER;
-- purpose: Implement main architecture of PAR2SER
architecture BEHAVIOR of PAR2SER is
signal IDATA : std_logic_vector(7 downto 0); -- internal data
begin -- BEHAVIOR
-- purpose: Main process
process (CLK, RESET)
begin -- process
-- activities triggered by asynchronous reset (active high)
if RESET = ’1’ then
SDOUT <= ’0’;
IDATA <= "00000000";
-- activities triggered by rising edge of clock
elsif CLK’event and CLK = ’1’ then
case MODE is
when "00" => -- no operation
null;
when "01" => -- load operation
IDATA <= DIN;
when "10" => -- shift left
SDOUT <= IDATA(7);
for mloop in 6 downto 0 loop
IDATA(mloop+1) <= IDATA(mloop);
end loop; -- mloop
when others => -- no operation otherwise
null;
end case;
end if;
end process;
end BEHAVIOR;
The author apparently regarded it useful to control serializer operation with a mode input. There are other options, too. You have to know your requirements.
But the code has a syntactical error, cause mode input is a single std_logic bit but used as a vector. It can't compile as is.
True what FvM says.
Moreover I've to tell you that this is a very bad way of code VHDL.
The construct FOR shall never being used: that's not "C".
You can do in a lot of different manner, the better I think is instantiate a counter and use a shift register.
In VHDL you've to figure out what are you realizing with the Flip Flop.