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Need Help in compiling VHDL using XILINX ise 9.2i

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ahyuanz

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Really appreciate if who could help me

here is the problem :

My project is to create a stopwatch.

The syntax is ok. However, when i am creating timing constraints... it fails to synthesize and prompt me this error : Signal MOD10CARRY_temp cannot be synthesized, bad synchronous description.

I am really at my wits end.. could not solve the problem.

i have uploaded my file to mediafire for your reference.

this is the url : http://www.mediafire.com/download.php?ffzw1mzidlt
 

farhada

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Hi,
I am not sure what you want to do but this part of your code is definitely not right:
Code:
process (CLK, RES, SET,UP_DN) 
begin
   if RES ='0' then 
     MOD10OUT_temp <= (others => '0');
	  MOD10CARRY_temp<= '0';
   
	elsif rising_edge(SET) then   
		MOD10OUT_temp <= MOD10OUT_temp+1;
		if MOD10OUT_temp = "1010" then
         MOD10OUT_temp <= "0000";
		end if;
			
	elsif rising_edge(CLK) then
		if UP_DN ='1' then
			MOD10OUT_temp <= MOD10OUT_temp+1;
			if MOD10OUT_temp = "1010" then
				MOD10OUT_temp <= "0000";
				MOD10CARRY_temp <= '1';
			else
				MOD10CARRY_temp <= '0';
				
			end if;	
		else
			MOD10OUT_temp <= MOD10OUT_temp-1;
			if MOD10OUT_temp = "1111" then
				MOD10OUT_temp <= "1001";
				MOD10CARRY_temp <= '1';
			else
				MOD10CARRY_temp <= '0';
				
			end if;	
		end if;

	end if;
end process;
I am sure if you split this process into 2 different process and only use on clock in the process your code will synthesize without any problem.

If I was you, I would check for the value of set, and as long as set is active, I set the value of the counter to the value requested and when the set is '0' then you count as normal.

Best regards,
/Farhad
 

chaoui

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Look at the piece of code posted by Farhad. You will note that MOD10CARRY_temp is set to '0' in the if statement however, it is not assigned a value in the else statement.

I hope this will help u.
 

farhada

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Ok, this is the 3rd time I a m trying to send this, hopefulyl it will work!

If you think in HW terms, you are trying to control the output of the signals in the process by 2 different clocks.
It is like implementing a flip-flop with 2 clock inputs.

I am really surprised that you could simulate this, and the error message from XST is not helpful at all.

BR,
/Farhad Abdolian
 

palai_santosh

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As Farhad said when you write like this its like driving a fip-flop with 2 clocks.
From the look of it , what i can see is the SET signal not required to be edge sensitive.
You can try somethign like this ( it will synthesize).

if you want it to be asynchronous set then you can do something like shown below.
if you want it to be synchronous then you can put the SET portion inside the clock
process (CLK, RES, SET,UP_DN)
begin
if RES ='0' then
MOD10OUT_temp <= (others => '0');


elsif SET='1' then
MOD10OUT_temp <= MOD10OUT_temp+1;
if MOD10OUT_temp = "1010" then
MOD10OUT_temp <= "0000";
end if;

elsif rising_edge(CLK) then
if UP_DN ='1' then
MOD10OUT_temp <= MOD10OUT_temp+1;
if MOD10OUT_temp = "1010" then
MOD10OUT_temp <= "0000";
MOD10CARRY_temp <= '1';
else
MOD10CARRY_temp <= '0';

end if;
else
MOD10OUT_temp <= MOD10OUT_temp-1;
if MOD10OUT_temp = "1111" then
MOD10OUT_temp <= "1001";
MOD10CARRY_temp <= '1';
else
MOD10CARRY_temp <= '0';

end if;
end if;

end if;
end process;
MOD10CARRY <= MOD10CARRY_temp;
MOD10OUT <= MOD10OUT_temp;

end Behavioral;
 

ahyuanz

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sorry for troubling you guys. My intention was to actually use 'set' to manually increase the value in the counter using a push button, that is why i use edge trigger.

So can it still work the way i want it to if i follow the code palai_santosh suggest by using logic 1 or 0 ?
 

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