`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:56:40 07/21/2017
// Design Name:
// Module Name: neuron
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
// 3.306 = 0000001101001110 w11
// 3.155 = 0000001100101000 w21
// 1.823 = 0000000111010011 w21
// 2.820 = 0000001011010010 w22-- bin(fi(2.820,1,16,8))
// -0.986 = 1111111100000100 b1
// 2.051 = 0000001000001101 b2
//////////////////////////////////////////////////////////////////////////////////
module neuron #(parameter NB=16,
w11=16'b0000110100111001,//3385,
w12=16'b0000011101001011,//1867,
w21=16'b0000110010011111,//3231,
w22=16'b0000101101001000,//2888,
b1=16'b1111110000001110,//-1010,
b2=16'b0000100000110100)(//2100 )(
input clk,
input rst,
input [NB-1 : 0] x1,
input [NB-1 : 0] x2,
output reg ready,
output reg [2*NB-1 : 0] y1,
output reg [2*NB-1 : 0] y2);
wire [2*NB-1 : 0] product1;
wire [2*NB-1 : 0] product2;
wire [2*NB-1 : 0] product3;
wire [2*NB-1 : 0] product4;
wire [2*NB-1 : 0] out_add1;
wire [2*NB-1 : 0] out_add2;
wire en1;
wire en2;
wire en3;
wire en4;
reg en13, en24;
FP_mult uut1 (
.clk(clk),
.rst(rst),
.multiplicand(x1),
.multiplier(w11),
.ready(en1),
.product(product1));
FP_mult uut2 (
.clk(clk),
.rst(rst),
.multiplicand(x1),
.multiplier(w12),
.ready(en2),
.product(product2));
FP_mult uut3 (
.clk(clk),
.rst(rst),
.multiplicand(x2),
.multiplier(w21),
.ready(en3),
.product(product3));
FP_mult uut4 (
.clk(clk),
.rst(rst),
.multiplicand(x2),
.multiplier(w22),
.ready(en4),
.product(product4));
// adder
FP_add #(9,22) uutA1 (
.en(en1 & en3),
.in1(product1),
.in2(product3),
.out_add(out_add1)
);
FP_add #(9,22) uutA2 (
.en(en2 & en4),
.in1(product2),
.in2(product4),
.out_add(out_add2)
);
FP_add #(9,22) uutA3 (
.en(en13),
.in1(out_add1),
.in2({{16{b1[15]}},b1}),
.out_add(y1)
);
FP_add #(9,22) uutA4 (
.en(en24),
.in1(out_add2),
.in2({{16{b2[15]}},b2}),
.out_add(y2)
);
always @ (posedge clk)
if (en1 && en2 && en3 && en4) begin
ready <= 1'b1;
en13 <= en1 & en3;
en24 <= en2 & en4;
end
else begin
ready <= 1'b0;
en13 <= 1'b0;
en24 <= 1'b0;
end
//assign y2 = product2 + product4 + b2;
//assign ready = (en1 && en2 && en3 && en4) ? 1'b1 : 1'b0;
endmodule