// Test Bench is written
module t_first;
reg t_a,t_b;
wire t_c;
first M1(t_c,t_a,t_b);
initial
begin
#5000 $finish;
end
initial
begin
t_a=0;
t_b=0;
#1000 t_a=1;t_b=1;
#1500 t_a=0;t_b=0;
end
endmodule
Your simulation only runs for 1000 ns, which incidentally is the default setting in ISE 12.3 for a simulation run. You can change it in Process => Process Properties => Simulation Run Time.