john6794
Newbie level 6
dear thanks.yes those all are primitive.and now i have complied it and got just one warning.its ok.
now problem is how i can generate its test bench in xilinx. if someone have prepared test bench for async FIFO.plz send
or
tell me how i can genrate it in vhdl
tks
now problem is how i can generate its test bench in xilinx. if someone have prepared test bench for async FIFO.plz send
or
tell me how i can genrate it in vhdl
tks