Need Help: Current Mirror Design

[waiheng318]

I'm new to circuit design as well as the current mirror design.

I'm using 2 different PMOS (1.2V & 2.5V) to design the current mirror circuit. Both bulk/body are sharing the same connection, while the Gates are connected to the same node.

My question is:

1. Can these 2 PMOS sharing the same NWell? Why?

Please help. Many thanks.

 

[stefano2m]

The bulk (substrate) connection are shorted, so it is clear that you can put the transistors in the same N-well.
Of course, you can place the transistors in separate N-wells, and connect by metal the two n-wells. There is no electrical advantage for this approach. In addition, the disadvantage is the area increase. Layout design rules ask, in general for quite big distance between two separate n-wells. This comes from technology - n-well is a deep implant, with long annealing time, therefore big diffusion after the implant.

The second disadvantage is mismatch. Placing the transistors in separate n-wells ould result in a big distance between them, therefore bad matching.

Have fun!

Added after 2 minutes:

Reading more carefully your question, I have a question:
Why do you want to build a current mirror with two different transistor type?

Is better to build the mirror using only one type (better matching), in you case, probably because of voltage constraints, 2.5V type.

 

[dalraist]

I do not think the matching is a problem: since the 2 PMOS has different oxide thikness, they are completely diffent by constraction.
To place them in the same well is possible, but you have to make sure that the Vgs of the low voltage device never exceeds 1.2V (or at least 1.4V), otherwise it will blow up.

 

[pbs681]

I'm new to circuit design as well as the current mirror design.

I'm using 2 different PMOS (1.2V & 2.5V) to design the current mirror circuit. Both bulk/body are sharing the same connection, while the Gates are connected to the same node.

My question is:

1. Can these 2 PMOS sharing the same NWell? Why?

Please help. Many thanks.

My opinion u cannot share the nwell. If you use 1.2V for both transistor, there is a possibility that S/D to body diode froward bias. And if you use 2.5V well, u might have problem with reverse bias BV of the same diode stated above.

 

[dalraist]

As far as I know different transistor voltages do not imply different wells, but different oxide thickness only.
So, if you use 2.5V for both transistors you may blow up the 1.2V transistor if Vds > 1.3V or Vgs > 1.3V.
If you use 1.2V for both you may have the 2.5V transistor in linear region instead saturation.

 

[pbs681]

As far as I know different transistor voltages do not imply different wells, but different oxide thickness only.
So, if you use 2.5V for both transistors you may blow up the 1.2V transistor if Vds > 1.3V or Vgs > 1.3V.
If you use 1.2V for both you may have the 2.5V transistor in linear region instead saturation.

If you check process documentation from foundry, beside the differnce for oxide thickness, the breakdown voltage (BV) for each well also different. This means that the transistors have different well. Also, the BVOX normally 2X voltage of the allowed VDD. That means the transistor will only blow if you apply 2(1.2)= 2.4V at the gate, not 1.3V. Same goes for BVDSS.

 

[waiheng318]

Thanks every one for the reply!

Lets discuss a more basic and simple current mirror circuit, for RF IP.

I'm going to use just the 1.2V RF PMOS type to build the current mirror.

1. Can I put all the PMOS in the same NWell? From my understanding above, Yes.
2. Can I round ALL the PMOS using a single N+ guard ring or must seperate for each PMOS. Any impact on the RF performance?

Please educate. thanks.

 

[prashantbabu]

To your last question - because the PMOS transistors are mirrors and you will be connecting all their bulks to the same potential, yes, you can put all the 1.2V PMOS transistors in the same n-well. But avoid putting a separate ring around each individual transistor.
Rather, you should take care to see that there is good matching between them(ex:interdigitisation).
So i suggest you first match the transistors, surround all the transistors with a single n-ring and put them all in one big n-well.
Hope this helps.