wtr
Full Member level 5
Hello all,
Situation is a follows.
Design in Vivado 2018.4
Have multiple signals going from clock domain A to clock domain B. I have created a synchronising FF to handle these signals. Furthermore I've created an entity that structurally instantiates the collection of sync'ing FF required to {clock domain crossing (CDC) or cross clocking domain (CCD)}.
Vivado has reported the following - inter-clock path failures. INTERESTING the reported inter-clock paths is an incomplete list. I have no doubt vivado will add more warnings after I've fixed only some of the startpoint/endpoints.
Now I have two options either set_max_delay or set_clock_groups -ascyn. Please inform me if I have more. [I never used set_multicycle_path etc].
The problem I'm having is the following.
1. I could explicitly go through and create a startpoint to endpoint constraint
2. I could set a constraint based on the clock domain x to clock domain y.
The problem with 1. is that its' tedious. The problem with 2. is that it creates a filter that could ignore signals that I forgot to place into FF-sync.
Therefore I have experimented with Vivados commands to "TRY" filter a result that is more specific.
Using the following
I can get a dump of the pins used in the entity
Using the following
I can get a dump of the clocks used in the entity
Now the crux of the problem, I cannot -do not know how to- filter the pins for a specific clock. Report_property xxx_pin/D will return a table but not specify what clock domain it belongs to.
Concluding the question
I would like to
set max delay -from all pins of clock type axi_aclk located in cell(read entity) sync_pcie -to all pins of clock type clk_125... located in cell(read entity) sync_pcie
and vice a versa.
Situation is a follows.
Design in Vivado 2018.4
Have multiple signals going from clock domain A to clock domain B. I have created a synchronising FF to handle these signals. Furthermore I've created an entity that structurally instantiates the collection of sync'ing FF required to {clock domain crossing (CDC) or cross clocking domain (CCD)}.
Vivado has reported the following - inter-clock path failures. INTERESTING the reported inter-clock paths is an incomplete list. I have no doubt vivado will add more warnings after I've fixed only some of the startpoint/endpoints.
Now I have two options either set_max_delay or set_clock_groups -ascyn. Please inform me if I have more. [I never used set_multicycle_path etc].
The problem I'm having is the following.
1. I could explicitly go through and create a startpoint to endpoint constraint
Code:
set_max_delay -from [get_pins {b_comms.u_comms/u_pcie1/u_sync_pcie/sync_addr/G1.sig_a_int_reg[0]/C}] -to [get_pins {b_comms.u_comms/u_pcie1/u_sync_pcie/sync_addr/sig_b_int_reg[0][0]/D}] 8.0
Code:
set_max_delay -datapath_only -from [get_clocks -of_objects [get_pins b_comms.u_comms/u_pcie1/u_pcie/inst/pcie3_ip_i/U0/gt_top_i/phy_clk_i/bufg_gt_userclk/O]] -to [get_clocks -of_objects [get_pins b_system_clocks.u_sys_clocks/G_clk.clk_tree_inst/inst/mmcme3_adv_inst/CLKOUT0]] 8.0
The problem with 1. is that its' tedious. The problem with 2. is that it creates a filter that could ignore signals that I forgot to place into FF-sync.
Therefore I have experimented with Vivados commands to "TRY" filter a result that is more specific.
Using the following
Code:
get_pins -of_objects [get_cells b_comms.u_comms/u_pcie1/u_sync_pcie]
Code:
b_comms.u_comms/u_pcie1/u_sync_pcie/CLK b_comms.u_comms/u_pcie1/u_sync_pcie/D[0] b_comms.u_comms/u_pcie1/u_sync_pcie/D[10] ...
Using the following
Code:
get_clocks -of_objects [get_cells b_comms.u_comms/u_pcie1/u_sync_pcie]
Code:
axi_aclk clk_125m8d8_clk_tree
Now the crux of the problem, I cannot -do not know how to- filter the pins for a specific clock. Report_property xxx_pin/D will return a table but not specify what clock domain it belongs to.
Concluding the question
I would like to
set max delay -from all pins of clock type axi_aclk located in cell(read entity) sync_pcie -to all pins of clock type clk_125... located in cell(read entity) sync_pcie
and vice a versa.