Need for cell aware ATPG for finfet technology.

[ranger01]

What is the need to generate ATPG patterns targeting the internal faults of a standard cell? Isn't it enough if we could just target the faults outside the cells? I agree that with decreasing technology node and newer transistor models, the defect level would increase. But how should the traditional ATPG get adopted to the changing technology node?

 

[maulin sheth]

When we move towards lower technology node, We need to target transistor level faults. Because by using transistor level fault models, we can target transistor only instead of Gate. Now, gate level faults are not enough, if we want more testability and coverage.

 

[ranger01]

Ok. Now I have a basic doubt. I completely understand the need for 3 types of DFT fault models viz., stuck-at, transition faults and path delay. If we can generate the patterns targeting these faults then isn't it sufficient to say if a cell/interconnect has manufacturing defect or not ? In my opinion ultimately that's the goal of DFT. Then we can blame it on foundry.

 

[maulin sheth]

Yea. That is true. We can blame on foundry. But By the way, we need synchronization between foundry and us. Now, these 3 types of fault models are sufficient. But for lower nodes, we need to target Cell aware, as we can have info about the particular transistor itself. Just to increase more testabilitty, now dft methods goes into the direction of Cell Aware.

 

[ranger01]

I have not worked on cell Aware ATPG, but my wild guess is that "just to increase more testability", would result in significant increase in the fault sites, hence the test time. If you look at the level of gate level abstraction I think we can collapse the internal faults using equivalence or dominance. May be I can rephrase my question as follows., " What are the different types of faults that are expected to appear within standard cell, which gets manifested in a completely different way than the traditional fault models?"

 

[rushabh007]

It has the same faults like bridging open . bridging short but that is inside the standard cell.. so it can not be detected by traditional fault models, as these models can only detect faults at the gate terminals not the inside the gate(cell)

 

[rca]

Well, in our company we used the UDFM from Mentor, tool which generate the fault based on the GDS/CIR of the std cell, and this list could be used by Tessent ATPG tool of Mentor.
One group tried on a 0.35um technology, which is not a so "small" node, by using this UDFM fault list instead a "usual" fault list which has reached a 99.3% stuck coverage.
With the UDFM, they have a similar coverage, but it reduced by 9ppm, which means the UDFM has detected 5 more failling parts, than the conventional stuck found, over 535'000 parts. As this is for automotive target application, that's in good way.

 

[rushabh007]

Yeah.. rca is true.. mainly cell aware is used to improve reliability & quality of device.. so that we must get lower DPM(defective parts per million)..

 

[ranger01]

Thanks rca and rushabh for your informative responses. I am not exposed to distinctive requirements for testing methodology in my small career. But IMHO in a given timing path (generic case) if the pins of the gates are covered using stuck-at pattern and/or transition pattern and the paths are covered using path delay models, isn't it enough to say that we have gained full coverage on that timing path ? Basically what kind of defects demand Cell Aware ATPG / UDFM is my question. Please educate me or provide me any reference papers if that is more useful.