Need clarification of VHDL syntax: delcaring component

[presto]

Is VHDL so wordy?

I'm newbie to VHDL. I used Verilog before. So my opinion might be wrong.

However, do I have to declare "component" when using an "entity" + "architecture" pair in another "architecture"? And if it has to be so, what if during the development, the "entity" needs changing from time to time, then I have to manually update the "component" delaration as well?

Any clarification is highly appreciated.

 

[omara007]

Re: Is VHDL so wordy?

u can't do any change in the entity of a sub-component .. and yes u have to instantiate the sub-component in the higher level comp. architecture ..

all u can do is to leave some sub-component ports floating while instantiated in a higher level component ..

 

[roger]

Re: Is VHDL so wordy?

I'm newbie to VHDL. I used Verilog before. So my opinion might be wrong.

However, do I have to declare "component" when using an "entity" + "architecture" pair in another "architecture"? And if it has to be so, what if during the development, the "entity" needs changing from time to time, then I have to manually update the "component" delaration as well?

Any clarification is highly appreciated.

You can write a perl script to read the sub-entity in some dir and then
write the sub-entity header to a package, include the package file in your
top file, then you won't need to modify them manually.

 

[maestor]

Re: Is VHDL so wordy?

Hi,

I would suggest to have a package with all the component definitions and then you just 'use' it when needed.

So you add...

library work;
use work.project_pkg.all;
use work.project_comps.all;

in the file where u r going to instantiate an entity.

-maestor

 

[the_penetrator]

Re: Is VHDL so wordy?

presto says:
> in VHDL - do I have to declare "component" when using an "entity" +
> "architecture" pair in another "architecture"?

That's legal VHDL. You don't have all this, though. You can declare all components in a "package" and include in the entity-architecture files without rewriting the component declarations.

I believe that verbosity has to do with Ada or possibily with the model of elabaration that is used by the VHDL compilation tools.

> And if it has to be so, what if during the development, the "entity" needs > changing from time to time, then I have to manually update the
> "component" delaration as well?

If you change the entity, you change your module's ports, so you naturally have to update the corresponding component as well. However, in many cases, you can reuse generic entity+architecture by using generics, global parameters (in a package), generate statements.

You can also have different architectures for the same entity, and you set for each instantiated "port map" the specific implementation you want with a "configuration".

I know it sounds verbose compared to Verilog but this is not necessarily a minus. Recall the ***bad*** type handling in Verilog, the lack of multi-dimensional arrays and so and so long. All these things that SystemVerilog is STEALING off from VHDL to produce a better Verilog.

A great PLUS of Verilog is the simplicity of the language: Easier parsers, easier tools....

the_penetrator©

 

[Aser]

Re: Is VHDL so wordy?

Many things which seem to be ambiguous in VHDL
serve to save time to look for errors in many usual cases.
Entity interface also does.
Besides, I like VHDL for its word register immunity.

 

[the_penetrator]

Re: Is VHDL so wordy?

Aser: i agree a lot with you.

I did Verilog 6 years ago and started learing VHDL since 2000. I am a VHDL fan due to its type consistency and that almost none of the Verilog ambiguities.

A good Verilog probably will be (is) SystemVerilog since it features some good new features, and a lot of the good VHDL stuff as well.

If properly used, VHDL ***is*** historically the first system design language. Maybe not that capable for this purpose as SystemC but there are a lot of early efforts of using it that way. Take a look at the historical 1992-1997 papers contributed at the VIUF site (search with Google, i don't recall the link).

cheers

the_penetrator©

 

[presto]

Re: Is VHDL so wordy?

Thank you guys for the input.

I still feel VHDL so ... ... , maybe I was indulged by the Verilog flexibility.

However, I wondered how to do this in VHDL:

In Verilog, I use #ifdef ... #endif to make the top module code suitable for both simulation and synthesis. Can I do the equivalent thing in VHDL? Text book told me an "entity" can have different "architecture" for different purpose. In this case, simply the "entity"-ies for simulation and for synthesis are different, although functionally they are same. For example, a simulation module gets its input from a file and a synthesis module gets its input from the pins. Any suggestion?

 

[the_penetrator]

Re: Is VHDL so wordy?

presto says:
> I wondered how to do this in VHDL:

OK, go ahead.

> In Verilog, I use #ifdef ... #endif to make the top module code suitable > for both simulation and synthesis. Can I do the equivalent thing in
> VHDL?

Yes. With conditional generate statements. It's easy and powerful. I do this a lot (include or not a specific module, or selected between completely different modules)

> Text book told me an "entity" can have different "architecture" for
> different purpose. In this case, simply the "entity"-ies for simulation
> and for synthesis are different, although functionally they are same.

Just the architectures (may or may not) differ.

> For example, a simulation module gets its input from a file and a
> synthesis module gets its input from the pins. Any suggestion?

I have done this a lot with instruction memory initialization. I have a string generic and some simulation-specific code. For simulation i read the specified file. For synthesis, you have to exclude this part from compilation (with synthesis tool pragmas) or you can also do this with generates... But i think the first method is more preferred here.

Check also the LPM (library of parameterized modules) used by Altera FPGAs. Xilinx also has something similar. The LPM has loadable memory elements (file initialization) for simulation. The same elements are used for synthesis. Also in FPGAs you can preload memories from the bitstream, but this is not portable VHDL.

cheers

the_penetrator©

 

[DJ_Dream]

Is VHDL so wordy?

Yeah - VHDL and Verilog are different languages but with the same concept !DJD