Re: Is VHDL so wordy?
presto says:
> in VHDL - do I have to declare "component" when using an "entity" +
> "architecture" pair in another "architecture"?
That's legal VHDL. You don't have all this, though. You can declare all components in a "package" and include in the entity-architecture files without rewriting the component declarations.
I believe that verbosity has to do with Ada or possibily with the model of elabaration that is used by the VHDL compilation tools.
> And if it has to be so, what if during the development, the "entity" needs > changing from time to time, then I have to manually update the
> "component" delaration as well?
If you change the entity, you change your module's ports, so you naturally have to update the corresponding component as well. However, in many cases, you can reuse generic entity+architecture by using generics, global parameters (in a package), generate statements.
You can also have different architectures for the same entity, and you set for each instantiated "port map" the specific implementation you want with a "configuration".
I know it sounds verbose compared to Verilog but this is not necessarily a minus. Recall the ***bad*** type handling in Verilog, the lack of multi-dimensional arrays and so and so long. All these things that SystemVerilog is STEALING off from VHDL to produce a better Verilog.
A great PLUS of Verilog is the simplicity of the language: Easier parsers, easier tools....
the_penetrator©