Need a power-on-reset solution

[Alan_Nesta]

1.5v vdd, when power up to 0.9v, reset can stop,
and when power fall down below 0.6v and re-power-up,
still need to generate a reset

Help!!!

 

[s_rampage]

If you elaborate your question a bit ,I may help you.

 

[xieyan2001]

You need two comparator:

one comparator is used to control the up-limit.
the other control the low-limit.

 

[Alan_Nesta]

vdd is power-uping, no vdd how to generator reference voltage?

 

[tsanlee]

1.5v vdd, when power up to 0.9v, reset can stop,
and when power fall down below 0.6v and re-power-up,
still need to generate a reset

Help!!!

You can use VTH of PMOS(09.V) and NMOS(0.6V).
,And tune its w/l.

 

[huojinsi]

u can design a schmitte comparator,set two steady state of schmitte is 0.9V, 0.6V respectively.