Need a power-on-reset solution

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Alan_Nesta

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1.5v vdd, when power up to 0.9v, reset can stop,
and when power fall down below 0.6v and re-power-up,
still need to generate a reset

Help!!!
 

If you elaborate your question a bit ,I may help you.
 

You need two comparator:

one comparator is used to control the up-limit.
the other control the low-limit.
 

vdd is power-uping, no vdd how to generator reference voltage?
 

Alan_Nesta said:
1.5v vdd, when power up to 0.9v, reset can stop,
and when power fall down below 0.6v and re-power-up,
still need to generate a reset

Help!!!
Click to expand...

You can use VTH of PMOS(09.V) and NMOS(0.6V).
,And tune its w/l.
 

u can design a schmitte comparator,set two steady state of schmitte is 0.9V, 0.6V respectively.
 

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