hareharan
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can anyone share me a sample program on encoder logic in verilogA.if any one could help me out with a example for 2 or 3 combinations at least using a "if" statement or a case statement would help me to understand better.
how do I represent bits in verilogA , for ex in vhdl we write in_ std_logic_vector[3 downto 0]; later when we write process(s) and case statement when "000"=>I<="0000001".the bits in the case statement gets mapped to vector statemnt .how can I do like this in verilogA?
Thanks in advance
how do I represent bits in verilogA , for ex in vhdl we write in_ std_logic_vector[3 downto 0]; later when we write process(s) and case statement when "000"=>I<="0000001".the bits in the case statement gets mapped to vector statemnt .how can I do like this in verilogA?
Thanks in advance
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