ankit12345
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It is Synopsys's Buzz word to denote thier "native compiled testbench (NTB), assertion and coverage" technologies. When it was started (guess 4 years back), SV was not around, so they supported OpenVera language and NTB was used as another "tool" instead of stand alone Vera tool. Vera as a tool can work with multiple simulators (NC, MTI, VCS), whereas NTB can only be used with VCS AFAIK.ankit12345 said:What is native testbench?????
How to use it????
What about Systemverilog????Is it better to use NVTB for SV????
ankit12345 said:In sv
Im implimenting verification using modules,not progam........
Its not full sv env.Its a mixture of sv and v.
I have class in one module and I want to creat objects in other module.
How to do that????
can hirarchial path supports????
any other solution???
ankit12345 said:Declared event in SV top module.
Im trying to use it in progam.
Can I????
In sequencess.....why events are not used????
modelsim62c said:Ajeetha:
You mentioned "Native Test Bench" (NTB)
Forgive me for asking a 2nd time, but is this a Synopsys designed methodology?
Or is it just a marketing buzzword to describe Synopsys's advanced simulator architecture? (I.e., the fact that it was native-compiled and executed on the host-machine at full-speed, unlike "emulated" programs which suffer through overhead of the PLI/VPI interface.)
I'm just trying to get a perspective of what we have today (IEEE Systemverilog 1800-2005) versus what was offered 3-4 years ago...
sujittikekar1 said:Can anybody suggest me the good book for system verilog for verification.. I am the begainer.So i want to start with basics of system verilog...
sujittikekar1 said:Can anybody suggest me the good book for system verilog for verification.. I am the begainer.So i want to start with basics of system verilog...
ankit12345 said:What is native testbench?????
How to use it????
What about Systemverilog????Is it better to use NVTB for SV????
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