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NANOSIM -- HSpice netlist and VERILOG netlist simulation

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tok47

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Hi ALL,


Recently, I faced a probelm when using NANOSIM.

First, I have a Spice top-netlist.

In this netlist, I will define all the analog blocks. And also call some digital blocks.

And those digital blocks were define in another VERILOG netlist.

How should I run my simulation?
I keep getting the error below. I dont know how to solve.

ERROR:NanoSim:0x30204008:cannot find subcircuit definition or function model
pipe_interface for instance X_PIPE_INTERFACE0.
nanosim: ERROR: Building instance tree failed. Program exits.


Thanks



Rdgs
YY
 

There is some problem when you build your tree structure.
Have you included the verilog netlist file in your top level netlist?
Check your netlist structure to see how your port between analog and digital are connected together.
 

Thanks for your reply.
I found the wrong coneection.
But, now another issue.... :p
Found port mismatch between SPICE netlist and verilog netlist.

The simulator can't read in this in the verilog netlist.
wire \CH0_VSP_STATUS[2] ;
wire \CH0_VSP_STATUS[3] ;
wire \CH0_VSP_STATUS[6] ;
wire \CH0_VSP_STATUS[7] ;

So, keep complaint that my SPICE netlist can't found CH0_VSP_STATUS[5].
 

i want a netlist file for simulation A full adder with HSPICe
 

I am also looking for a netlist for an adder in hspice. please help
 

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