nand layout in cadence plz help me

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mytreyi

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I was implemented nand gate layout in cadence tool....is it correct or not...
one body (M1_pDiff for nmos,M1_Nwell for PMOS) is enough for all nmos(pmos) circuits in the design...
how to connect the substrate....
IN schematic all nmos body connect to the gnd,all pmos connect to the supply vdd....
just i am in starting stage.. layout in cadence..plz help me...
 

use pwell contact to connect pwell to ground
Nwell contact to conect NWELL to Vdd
 

Is it required to two m1_nwell,m1_pdiff....
 


it is recommended to put M1_pDiff and M1_Nwell between the transistors and not beside them. try also to put more M1_pDiff and M1_Nwel to avoid latch-up.
 

See also ahata's StandardCell NAND layout in this thread (posting from Tue, 02 Mar 2010 15:29)
 
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Hi friend,

I have seen your layout, It is good, one thing you have to note is don't connect body connection to source terminals directly. what i mean is you to connect body connections and source connections to power supply lines individually.
More number of devices, the more body taps you have to lay.
And the area should be small.

thankyou,
~ raki
 

thak u for reply...
if many nmos transistors in series in the design...is it required to every nmos body connected to the gnd..one body is enough in the layout dsign
please tell me how to layout the resistor,capacitor in cadence tool...

thanq.....
 

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