Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

NAND latch with input (S=0 R=0)?

Status
Not open for further replies.
T

treez

Guest
Newbie level 1
Hello,

This is the forbidden state, so does it damage the latch?


eg does it make it oscillate its output wildly till it breaks?
 

Check the logic, do you see it oscillating? The output state might be unexpected or possibly unwanted, that's it.
 
  • Like
Reactions: treez

    T

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top