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n1os & m1croblaze, opinions ?

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sgrudu

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Yesterday @ltera annouced version 3.0 of n1os soft processor core. Also x1linx m1croblaze stuff
is in big development. It seems we'll see in the future lot of applications working with
these soft processors.
I've ordered an ins1ght xil1nx proto board and as soon as I can will give a try to m1croblaze,
but personally I like very much the fact that @ltera gives the GNUpro sources for n1os
for free without problems. Instead x1linx just sells the edk with a subset of GNUpro
precompiled only for windows... bleah.

I'd like to know opinions here from people who have tried one of these two processor
cores and had experience with that.

There are a lot of factors to take into account:
- processor performance
- fpga's supporting them and costs for fpgas.. (for example m1croblaze can run on
v1rtex-II pro but it can run on sp@rtan-II too.. )
- cost of: core / additionals ip cores / dev boards
- easy of use and power of development software
etc..

Greets

sgrudu
 

loki

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I haven't used the latest invocations of the Microblaze or Nios cores but I did try them both when they were first released.
From my experience, the NIOS core and software package is much, much, easier to set-up and use. I had a system running in a couple of hours with the core, parallel port interface, and multiple internal peripherals. Very easy to get started and well documented.
The microblaze core didn't seem as user friendly but if experience holds I would assume this core is more flexible and faster than the Nios. The software environment doesn't set-up easily and the coregen / invocation method is plagued with bugs that cause bizarre symptoms(typical with the Xilinx software tools). Xilinx has no problem letting you squirm due to buggy implementation software. That's why there are so many third party compilers out there.
A plus with the Microblaze is that they have a hard core (virtexII-pro) which follows a similar interface spec. as the soft core. So if you end-up looking for higher performance, the leap woul be easier in the future.

I would assume that Xilinx has improved thier system with later releases so I think you have the right idea to evaluate both of them.

Similar FPGAs in terms of size and speed are priced similarly in quantity. Xilinx tools seem to produce faster and smaller logic for the designs I've worked on, however.
 

Jayson

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I've never worked with soft processors, but I am interested in microblaze from Xilinx.

I have a couple questions, I have not been able to find these answers on Xilinx's website:

1) How does someone use the core? Do you just program it using Impact?

2) How does someone write a program? what language? where is it stored? is it stored in external flash? if so then how does the softprocessor use address and data? how does it know which pins are address and data since the FPGA is customizable?

3) Is a Xilinx 50K FPGA enough to store the whole contents of the core and still have enough left over for custom features? If not what is the target gate count in an FPGA for the softprocessor?

- Jayson
 

ddr

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loki said:
I haven't used the latest invocations of the Microblaze or Nios cores but I did try them both when they were first released.
From my experience, the NIOS core and software package is much, much, easier to set-up and use. I had a system running in a couple of hours with the core, parallel port interface, and multiple internal peripherals. Very easy to get started and well documented.
The microblaze core didn't seem as user friendly but if experience holds I would assume this core is more flexible and faster than the Nios. The software environment doesn't set-up easily and the coregen / invocation method is plagued with bugs that cause bizarre symptoms(typical with the Xilinx software tools). Xilinx has no problem letting you squirm due to buggy implementation software. That's why there are so many third party compilers out there.
A plus with the Microblaze is that they have a hard core (virtexII-pro) which follows a similar interface spec. as the soft core. So if you end-up looking for higher performance, the leap woul be easier in the future.

I would assume that Xilinx has improved thier system with later releases so I think you have the right idea to evaluate both of them.

Similar FPGAs in terms of size and speed are priced similarly in quantity. Xilinx tools seem to produce faster and smaller logic for the designs I've worked on, however.
Unfortunately for Xilinx, I must concur with Loki.
I'm afraid Xilinx has to put as much as 10x the effort into Microblaze to achieve the same level as Altera...too bad, maybe a missed opportunaty.
 

sgrudu

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Ddr, what do you mean with "level" ?
Level of what ?
Greets,

sgrudu.
 

ddr

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level = ?

sgrudu said:
Ddr, what do you mean with "level" ?
Level of what ?
Greets,

sgrudu.
Same level of quality:
*easy to work with
*bug-free
*short time to design
*good manuals

best regards,
ddr
 

ddr

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Answer to Jayson's question

Jayson said:
I've never worked with soft processors, but I am interested in microblaze from Xilinx.

I have a couple questions, I have not been able to find these answers on Xilinx's website:

1) How does someone use the core? Do you just program it using Impact?
You install Xilinx EDK kit 3.1 or the new 3.2. You run Xilinx Platform Studio and you configure you're very own Microblaze embedded system. You have to choose which peripherals you use, which buses (opb or plb), which memory ranges, and all the settings of the peripherals i.e. for the uart-lite you have to set the baud-rate and the frequency of the microblaze to set the internal divider.

Jayson said:
2) How does someone write a program? what language? where is it stored? is it stored in external flash? if so then how does the softprocessor use address and data? how does it know which pins are address and data since the FPGA is customizable?
You can write assembler code or c-code (maybe even c++, but i'm not sure) it can be stored in on-chip ROM or RAM or external SRAM, flash, SDRAM or DDR-RAM.
the addresses have to be set by the user in the "add/edit cores dialog"
all pins of external peripherals and memory first have to be defined in the "add/edit cores dialog" as a "port". in the pinning file (.ucf) you have to connect these internal ports to the outside physical world.

Jayson said:
3) Is a Xilinx 50K FPGA enough to store the whole contents of the core and still have enough left over for custom features? If not what is the target gate count in an FPGA for the softprocessor?
- Jayson[/quote]
I currently have a simple design with just 1 uart, 1 jtag-uart and 1 sdram-controller. I takes 19% in a Virtex-II 1000.
Theorectically it should be able to put it in a Xilinx 50K FPGA.

Best regards,
ddr
 

nitr8

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I hate this stupid EDk crap. I just bought a xilinx board with virtex II pro FPGA. I had to configure shit load of things and in the end it doesn't work. I called xilinx tech support and they say they have never heard of this board (which buy the way is available from xilinx website). that shitty tech support. I still unable to get those stupid tech support people to send me an example that works for XC2VP20.
no luck still now.


I'll stay clear of xilinx if i were u.
 

shekar_vlsi

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for me from design point of view nios is better
 

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