Jaraqui
Newbie level 5
Please consider a VHDL module which must behave according to the following scenario (clk = clock input; rst = assynchronous reset):
1) clk, rst --> module --> n-position vector with m-bits
2) n: I need sizes such as 20, ..., 50;
3) m: something like 4 or 8 bits
To reach this I developed the following code for a n-2, m-4 vector
This code works fine, but I think it is a kind of brute force. Generalizing it is pretty ugly.
Any ideias to do this in a clever way will be wellcome.
1) clk, rst --> module --> n-position vector with m-bits
2) n: I need sizes such as 20, ..., 50;
3) m: something like 4 or 8 bits
To reach this I developed the following code for a n-2, m-4 vector
Code:
--...piece of my_package...
type chr_type is array (1 downto 0) of std_logic_vector(3 downto 0);
type chr_counter is array (1 downto 0) of integer range 0 to 15;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.my_package.all; entity my_counter_chr is port( clk: in std_logic; rst: in std_logic; q_counter: out chr_type); end entity; architecture arch of my_counter_chr is begin process(clk, rst) variable counter: chr_counter := (0, 0); begin if(rst = '1') then counter := (0, 0); elsif(clk'event and clk = '0') then if (counter(0) < 15 and counter(1) < 15) then counter(0) := counter(0) + 1; elsif (counter(0) = 15 and counter(1) < 15) then counter(0) := 0; counter (1) := counter(1) + 1; elsif (counter(0) < 15 and counter(1) = 15) then counter(0) := counter(0) + 1; elsif (counter(0) = 15 and counter(1) = 15) then counter(0) := 0; counter(1) := 0; end if; end if; q_counter <= (std_logic_vector(to_unsigned(counter(1), 4)) , std_logic_vector(to_unsigned(counter(0), 4))); end process; end arch;
This code works fine, but I think it is a kind of brute force. Generalizing it is pretty ugly.
Any ideias to do this in a clever way will be wellcome.