Re: FATAL ERROR while loading design // ** Fatal: SDF files require Altera primitive
Seems you're missing the library for a primitive based on the error message. Did you start vsim with the correct -L <altera_primitive_lib_name> in the command?
Re: FATAL ERROR while loading design // ** Fatal: SDF files require Altera primitive
This is what i type : "vsim -sdftyp /instance/=C:/Users/designs/my_design.sdf work.my_design_tb"
Should i command this instead "vsim -L work -sdftyp /instance/=C:/Users/designs/my_design.sdf work.my_design_tb"?If so,then the same error occurs.The primitive library is the library that has the cells that my_design uses?Which library is it?
Re: FATAL ERROR while loading design // ** Fatal: SDF files require Altera primitive
Did you ever do this at some point previously? It kind of seems like the Altera tools expect the primitive libraries are already pre-compiled in their default location.
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I just noticed this is in the wrong section...I'll move it to the programmable logic section
Did you ever do this at some point previously? It kind of seems like the Altera tools expect the primitive libraries are already pre-compiled in their default location.
Well,i dont use FPGA i used Synopsys Design Compiler of ASIS to get the vhld gate-level netilist, that's why i think this is not necessairy.I think these precompiled models concern FPGA designs..
So why are you targeting this ASIC design to Altera libraries? If you want an Altera compatible netlist, compile it with Quartus. This is obviously why you are having problems, the netlist produce by DC probably don't have any matching primitives with Altera.
So why are you targeting this ASIC design to Altera libraries? If you want an Altera compatible netlist, compile it with Quartus. This is obviously why you are having problems, the netlist produce by DC probably don't have any matching primitives with Altera.
That is the problem,i do not think that i target any Altera libraries.The only library that i target is the technology library "fsd0a_a_generiic_core" of my design!I cannot understand why this message occurs..
This is the command i use vsim -L fsd0a_a_generiic_core -sdftyp /instance=my_design.sdf work.my_design_tb
You're obviously using something from Altera as the error is due to library primitives not matching. Are you using the Altera Modelsim (violating the license agreement) to run simulations on an ASIC design? That modelsim version is both slower than the regular Mentor product and is setup to use precompiled Altera libraries (if it's the free version). Compiling the ASIC simulation library will probably exceed the limits of the Altera Modelsim and it will likely take hours to even run 1us simulations.
You should be using the full version of Modelsim from Mentor.