sel1 is rasing edge and sel2 is falling while sel1 falling edge and sel2 is rasing edge
initial begin
sela = 1'b0;
selb = 1'b0;
end
always @ (posedge sel1) begin
sela <= not selb; // warning, must meet setup/hold
data_a <= data_1;
end
always @ (posedge sel2) begin
selb <= sela; // warning, must meet setup/hold
data_b <= data_2;
end
always @ (sela, selb, data_a, data_b) begin
if (sela^selb) begin
out = data_a; // warning, combinatorial output.
end else begin
out = data_b; // warning, combinatorial output.
end
end
Apparently, something gots confused here. Permute has worked out his own version of the logic, I'm not sure, if it's meeting the problem. You should better clarify what's actually intended.sel1 is rasing edge and sel2 is falling while sel1 falling edge and sel2 is rasing edge.
If you possibly want to latch one input on the rising clock edge and the other on the falling edge of a clock, than you could use a DDIO register
So Sel1 and Sel2 is actually DCO+/DCO- of the ADC. In this case, you should assign a differential I/O standard for the DCO input instead of combining them by logic, which isn't better than using one DCO line single ended.sel1 and sel2 is a pair of differential output from AD9481 which is a fast AD converter
I would use a simple asynchronous select as a multiplexer. But the question is, if the 250 MHz data should be registered to the 250 MHZ clock domain.is it simply enough to multiplex two 8 bits data bus to one 8 bits data output with DCO+/DCO- ????
Are you referring to a particular application problem?Two input how can be solved , but how about four input clocks ????
That's for sure. At the end, you'll need a chain of multiplexers to combine the four inputs to one output. To achieve this without timing violations, the relation of the "clock" and data signals, and their actual speed should be known.my code which give a multiple constant driver
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