There are two clocks in a design, when we are doing scan insertion, adding lockup latches for avoiding the Clock Skews. Is there any other method to avoid clock skew in multiple design other than lockup latch? please let me let know
There are two clocks in a design, when we are doing scan insertion, adding lockup latches for avoiding the Clock Skews. Is there any other method to avoid clock skew in multiple design other than lockup latch? please let me let know
If you take care of the skew between the two clocks while closing the testmode timning, you may aviod the lockup latch. But I am not sure about the silicon results.
yes this is rightly said, balancing both the scan clocks for the required skew limit should help and validating TEST STA for all the modes and corners and OCV(on chip variation) should aid your confidence of the design.
what do you loose having a lockup latch across the clocks ?
yah v have another method other than lookup latch is to mention pin as PRESERVE PIN in clock tree specification file so that clock tree algorithm makes best to reduce skew .......