culstar
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Hello everyone..
I have to design a 8x1 multiplexer using transmission gate logic at 800MHz frequency with 100fF load capacitance. I have already designed the circuit.
I am supplying input as Vsource with pulse waveform and period as 1.25 ns. But even at 2x1 multiplexer level with transmission gates, I am getting my output clipped.
Input = 0 to 1.8V
Vdd=1.88V
W/L(p)=12u/180n
W/L
=6u/180n
The output pulse varies from 0.75 V to 1.8V with some delay (Obviously).
Can you please help me to avoid this output clipping to get my output from 0 to 1.8 V with minimum delay time and area, as I also have to draw the layout diagram........
I have to design a 8x1 multiplexer using transmission gate logic at 800MHz frequency with 100fF load capacitance. I have already designed the circuit.
I am supplying input as Vsource with pulse waveform and period as 1.25 ns. But even at 2x1 multiplexer level with transmission gates, I am getting my output clipped.
Input = 0 to 1.8V
Vdd=1.88V
W/L(p)=12u/180n
W/L
=6u/180nThe output pulse varies from 0.75 V to 1.8V with some delay (Obviously).
Can you please help me to avoid this output clipping to get my output from 0 to 1.8 V with minimum delay time and area, as I also have to draw the layout diagram........
