input [width1-1:0] in1;
input [width2-1:0] in2;
input [width3-1:0] in3;
input [1:0] sel;
output [out_width-1:0] out;
Hi,
I do have a single data bus. The size for it is fixed. But the data that comes on it changes in width. Basically its an unaligned data because of the additional information that is added to it. Is there no way to implement this in hardware?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 parameter width1 = 8; parameter width2 = 16; parameter width3 = 32 always @(posedge clk) begin out <= 0; case (sel) 2'b 00 : out[0 +:width1] <= in1; 2'b 01 : out[0 +:width2] <= in2; 2'b 10 : out[0: +width3] <= in3; endcase end
Code Verilog - [expand] 1 2 3 4 5 6 7 always @(posedge clk) begin case (sel) 2'b 00 : in_slice1 <= out_data[0 +:width1]; 2'b 01 : in_slice2 <= out_data[0 +:width2]; 2'b 11 : in_slice3 <= out_data[0 +:width3]; endcase end
The second case I wrote above is not a mux I just use that type of syntax to improve the readability of the code instead of having a bunch of if statementsHi,
Thank you so much for your reply. Its really helpful. I tried implementing it in such a way that I have two back to back MUXs basically. So the output of the first MUX is of fixed width and goes to a second MUX which uses the same select inputs to decide what the final output will be (by truncating a certain number of bits). Is that sort of what you have done as well?
Code Verilog - [expand] 1 2 3 if (sel == 0) slice_8bit = out[7:0]; else if (sel == 1) slice_16bit = out[15:0]; else if (sel == 2) slice_32bit = out;
Hi,
Thank you so much for your reply. Its really helpful. I tried implementing it in such a way that I have two back to back MUXs basically. So the output of the first MUX is of fixed width and goes to a second MUX which uses the same select inputs to decide what the final output will be (by truncating a certain number of bits). Is that sort of what you have done as well?
This is basically connecting the output channel of a mux to the input channel of a demux. It is not going to be of any use because it is the same number of imput channels to the mux that you would have as output channels on the demux.
I was thinking you just meant to multiplex input data of varying width placed on a fixed width multiplexer while ignoring the channels that bear no information and then transferring the now serial data for remote use or so.
A mux has a single bit output. You can synchronize the output with clock though.
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If you just have a mux and then a demux, and you have a common select signal to the select inputs of both, then the bit into the channel0 of mux will exit at channel0 of demux, that at channel1 of mux will exit at channel1 of demux, and so on.
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You could just make a behavioral description of what you want instead of a structural connection of mux and demux. That's just my thoughts though.
Hi!
I will explain what I have done. I tested it and it works fine; I just want to know if there is a better way to do it.
My data bus is fixed; as i said. So my data comes in on a bus. I used case statement to determine what widths of data to chop and use. But again, the output needs to be a fixed width. so I end up with the desired output data with appended 0's on the excess width of the bus.
This I then send to another module (sort of like a DEMUX) along with the select signals. What I need to do in this module is add some extra information to my input data. So using the select input, I chop the data to desired width (basically remove the extra 0's that we got on the big bus) and append the desired data and send it out on a variable number of outputs. Basically implementing a DEMUX.
Everything works as expected. But is there any other way to do this?
This sounds like this question is related to your other question. https://www.edaboard.com/showthread.php?386638-parameterized-insertion-of-bits-to-data. Forum rules forbid this. Next time ask all related questions on the same topic in a single thread.
What you've described is exactly the way it should be done. A for loop will only make it harder to maintain the code as you are trying to be "clever".
So the data coming in on the bus has bits that are either '1', '0' or 'Z'?
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I'm much concerned about 'Z'.
Okay, so it's just parallel data comong in and not necessarily a bus.
Doing this operation using a mux and then a demux to me is time consuming. I believe the operation can be accomplished with even shorter time.
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If your aim is to minimize the time it takes to complete the operation, then I believe I can propose a solution for you.
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