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Multiple warning about signals and blocks being disconnected (verilog)

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wnr004

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Hey all,

I'm very new to programming for FPGA boards so I'm pretty lost.

I'm using a Spartan 3 board and developing in Verilog using Xilinx ISE. I have a bunch of warnings in my code like the following:
WARNING:Xst:737 - Found 4-bit latch for signal <display>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:1290 - Hierarchical block <a0> is unconnected in block <Calculator>.It will be removed from the design.
WARNING:Xst:2677 - Node <firstNum_0> of sequential type is unconnected in block <Calculator>.

My question is why are all these things being unconnected? In my code, all variables go to an output, and I think I cover all the cases in my IF and CASE statements. Please look at the following code and give me some advice. Thanks a ton.

MAIN MODULE:
module Calculator(
input FPGA_CLK,
input Ain, Bin, Cin, Din, //Hex pad
input RESET,
input ADDITION, SUB, MULT, DIV, //Switch 7-4
input EQUALS, //Switch 0
output A, B, C, D, E, F, G, AN3, AN2, AN1, AN0, //7 segment display
output vcc, gnd
);

assign vcc = 1;
assign gnd = 0;

parameter resetState = 2'b00;
parameter firstNumInputState = 2'b01;
parameter secondNumInputState = 2'b10;
parameter showAnswerState = 2'b11;
reg [1:0] state, nextstate;

reg [3:0] firstNum, secondNum, display;
wire [3:0] answer, keyPad;
assign AN3 = 1;
assign AN2 = 1;
assign AN1 = 1;
assign AN0 = 0;


algebra a0 (firstNum, secondNum, ADDITION, SUB, MULT, DIV, answer);
decoder d0(display, A, B, C, D, E, F, G);
keyPadInput k0(Ain, Bin, Cin, Din, keyPad);

//state transition
always @ (posedge FPGA_CLK, posedge RESET) begin
if (RESET)
state <= resetState;
else
state <= nextstate;
end

//next state logic
always @ (*) begin
case (state)
resetState:
nextstate = firstNumInputState;
firstNumInputState:
if (ADDITION | SUB | MULT | DIV)
nextstate = secondNumInputState;
else
nextstate = firstNumInputState;
secondNumInputState:
if (EQUALS)
nextstate = showAnswerState;
else
nextstate = secondNumInputState;
showAnswerState:
if (!EQUALS)
nextstate = resetState;
else
nextstate = showAnswerState;
default:
nextstate = resetState;
endcase
end

//state logic
always @ (*) begin
case (state)
resetState: begin
firstNum = 4'b0;
secondNum = 4'b0;
end
firstNumInputState: begin
firstNum = keyPad;
display = keyPad;
end
secondNumInputState: begin
secondNum = keyPad;
display = keyPad;
end
showAnswerState: begin
display = answer;
end
default: begin
firstNum = 4'b0;
secondNum = 4'b0;
end
endcase
end
endmodule

module algebra(
input [3:0] first, second,
input ADDITION, SUB, MULT, DIV,
output reg [3:0] answer
);

always @ (*) begin
if (ADDITION)
answer = first + second;
else if (SUB)
answer = first - second;
else if (MULT)
answer = first * second;
else if (DIV)
answer = first + second;
else
answer = 4'b0000;
end
endmodule

module decoder(
input [3:0] num,
output reg A, B, C, D, E, F, G
);

always @ (*) begin
case (num)
4'b0000: begin
G=1;
end
4'b0001: begin
A=1;D=1;E=1;F=1;G=1;
end
4'b0010: begin
C=1;F=1;
end
4'b0011: begin
E=1;F=1;
end
4'b0100: begin
A=1;D=1;E=1;
end
4'b0101: begin
B=1;E=1;
end
4'b0110: begin
B=1;
end
4'b0111: begin
D=1;E=1;F=1;G=1;
end
4'b1001: begin
E=1;
end
endcase
end
endmodule

module keyPadInput(
input A, B, C, D,
output reg [3:0] out
);

always @ (*) begin
out[3] = D;
out[2] = C;
out[1] = B;
out[0] = A;
end
endmodule
 

FvM

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At present, no code is generated for your design, because the decoder sets all outputs to 1 (only sets, but don't reset them).
Simply insert a line A=0;B=0;C=0;D=0;E=0;F=0;G=0; before the case statement to make the decoder work.

The code will be still inferring latches due to the design style. It brings up the risk, that the respective numbers get corrupted during state transition. You should think about assigning them in a clock edge sensitive always block instead.

Other warnings address the fact, that bits are cut in the multiplication.
 

wnr004

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Thank you so much, that solved it! I'm surprised I missed something so dumb. I come from a programming background so that's super embarrassing.
 

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