Multiple VHDL files and DES/AES Core

[Kid_Bengala]

aes vhdl

hi

I´m new to VHDL and attacked me two questions. The first is that I have fallen in some cores Opencore and I've seen that have multiple files. vhd. I had scheduled so far in any one know how to access various files and implemented in an FPGA.

The other question I have is to use a core from another core. So far I have planned little things, which included data on the one hand, makes a few changes and leave other pins. Let me explain, I have a code to access a flash memory, this is implemented in the FPGA and operates correctly, the problem is that this memory is encrypted with DES or AES, so I dropped from a cryptographic core Opencore but not How to make accessing the memory, the cryptographic core for this medium and decrypts the data (MEMORY -> DES CORE -> FLASH CORE). Any help or advice for this newbie in VHDL? . Thank you very much.

Greetings
Antony

 

[vipulsinha]

des vhdl

Hi Antony

As I understand from you post the answers to your questions are below.

You have downloaded the VHDl files for the Encryption algorithm .You will find that there will be a top level file that binds all the modules in the design. In VHDL we have top level ENTITY that has all the bus designed entities attached to it. All you need is to make a project. Include all VHDL files and locate the TOP LEVEL entitiy file and use this top level for simulation purpose.

Answer to second question is you will have to interface a interface between the memory and the DES/AES algo block that you have downloaded from Open Cores.

So it will take data from the flash---> Encrypt it with encryption block-----> store it in another memory. For this snother memory you will again have to design an interface block.

Hope this helps

Vipul