Multiple transistor instances in parallel in Mentor Pyxis

[rafauy]

Hi,

I am trying to do something that I thought it would be possible in Pyxis (schematic capture), but I cant find it in the reference manual. I have a bus BUS_123(63:0) of 64 bits and I want to create 64 equal transistors in which each gate is connected to one of the bits of the bus. Naming the instance PMOS_XXX(63:0) seems to work but I cannot make the connection from each bit to each gate. Does anybody know if this is possible (and how )?

Thank you!
R.

 

[dick_freebird]

I'm unfamiliar with that tool but others, you'd place the transistor
as PMOS_XXX(63:0) (iterated instance) and simply attach the bus
(named net, BUS_123(63:0) to "the" gate pin (which is also iterated).

Now breaking apart the other signals of the iterated instance (like,
say, if each of the drains had a different destination) you'd have
to attach a 64-wide bus, and then "rip" it (either a bus-ripper
symbol, or perhaps the tool allows you to take a single or sub-
bundle of wires out by attaching a plain wire (not bus) with (say)
BUS_123(59) label, or (say) a bus-wire with BUS_123(15:0) for a
bundle. The netlister ought to keep track of that "bookkeeping".