Multiple scan chain insertion in hierarchical design

[Syedaaa]

Hi,

We have a hierarchical design in which blocks are replica of each other. We want to have some strategy to insert scanchain in one block and then just replicate the blocks. This will reduce the ATPG pattern size and simulation/testing time on the other hand as we will be able to test all the scan chains at the same time in parallel. But the problem is how can we verify the paths connecting these similar blocks without stitching the scan chains in the top module? How can we verify that there is no manufacturing fault in the paths connecting these blocks? Can anyone suggest any solution to this problem?

Thanks in advance

 

[tepalia02]

One approach to verifying the paths connecting similar blocks without stitching the scan chains in the top module is to use a hierarchical test methodology. In this approach, you would perform a series of tests at the block level, and then verify that the connections between the blocks are functioning correctly at the top-level module.

Here are the steps you could follow:

1. Define a test plan for each block that includes scan chains, functional tests, and any other relevant tests. This test plan should include tests for the inputs, outputs, and internal signals of the block.
2. Verify each block using the test plan, and fix any issues found during verification.
3. Once all the blocks have been verified, integrate them into the top-level module.
4. Run a set of top-level tests that verify the connections between the blocks are functioning correctly. These tests should include functional tests that exercise the blocks as well as connectivity tests that verify the signals between the blocks.
5. Use manufacturing tests, such as stuck-at and transition fault tests, to verify that there are no manufacturing faults in the paths connecting the blocks.
6. Finally, run a full-chip scan test that exercises all the scan chains in parallel to ensure that the design meets the required test coverage.

By following this approach, you can verify the functionality of each block and the connectivity between the blocks without stitching the scan chains in the top module. This will reduce the ATPG pattern size and simulation/testing time while ensuring that there are no manufacturing faults in the paths connecting the blocks.