// Define Sobel operator kernels
localparam [2:0][2:0] x_kernel ={ "-1, 0, 1", "-2, 0, 2", "-1, 0, 1" };
localparam [2:0][2:0] y_kernel = { " -1, -2, -1 ", " 0, 0, 0 ", " 1, 2, 1 "};
i want to implement it on vivado zcu106 board for edge detection for image processing and add hdmi to itmultiple packed dimensions are not allowed in this mode of verilog.
Try something like this:// Define Sobel operator kernels
localparam [2:0][2:0] x_kernel ={ "-1, 0, 1", "-2, 0, 2", "-1, 0, 1" };
localparam [2:0][2:0] y_kernel = { " -1, -2, -1 ", " 0, 0, 0 ", " 1, 2, 1 "};
i am getting error multiple packed dimensions are not allowed in this mode of verilog.
i want to implement it on vivado zcu106 board for edge detection for image processing and add hdmi to it
thank you
{ {-1, 0, 1}, {-2, 0, 2}, {-1, 0, 1} };
Try something like this:
Code:{ {-1, 0, 1}, {-2, 0, 2}, {-1, 0, 1} };
how to declared can you please guide me?A regular array spec has the range declaration(s) after the identifier.
localparam x_kernel [2:0][2:0] ={ {-1, 0, 1}, {-2, 0, 2}, {-1, 0, 1}};localparam x_kernel [2:0][2:0]
localparam integer x_kernel [2:0][2:0] ='{ '{-1, 0, 1}, '{-2, 0, 2}, '{-1, 0, 1}};
The Vivado simulator supports a subset of SystemVerilog required by synthesis.i am using vivado
hi,The Vivado simulator supports a subset of SystemVerilog required by synthesis.
You have not answered why you do not use the SV switch during compilation!
I can only guess, make sure the sub-module sobel_operator is added to your project.Cell 'sobel_inst' of type 'sobel_operator' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
yes i have added it and it showing errorI do not have your project environment so I cannot tell what you are doing wrong unless you specifically show them here.
I can only guess, make sure the sub-module sobel_operator is added to your project.
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