Hello Everyone.
Can anyone help me in Multiple interface instantiation in the module and how to drive these interfaces.
here is the code :
// Interface File
interface intf_i(input clock);
logic[3:0]a ;
logic[3:0] b;
logic[5:0] c;
clocking cb @(posedge clock);
input a;
input b;
output c;
endclocking
modport MP (clocking cb, input clock);
endinterface
// DESIGN FILE
module abc (intf_i in[0:8], input clock);
genvar i;
generate
for(i =0; i <8; i++)
begin
always @(posedge clock)
begin
in.c = in.a + in.b;
end
end
endgenerate
endmodule
// Testbench File
`include "intf.sv"
`include "mod.sv"
module top;
bit clock =0;
always
begin
clock = #5 ~clock;
end
genvar i;
for(i =1; i<8; i++)
begin
intf_i in(clock);
abc ab(in, clock);
end
endmodule
but this code is showing some errors !!
Thanks