Multiple input and output port ROM

[SharpWeapon]

Hello,

For an FFT processor with N stages, I saved all the twiddle factors in one block ROM(which I think would be efficient than having multiple slices of ROM for each stage, don't you think? ), after reading one big file. Now, since the twiddle factors should be fetched in parallel for different butterflies working simultaneously I need a MULIT-PORT ROM capable of reading /outputting MULTIPLE memory address values at a time(NB: all the parallel readings are disjoint).

For instance, let us say the module has 16 addresses, each K bits, as inputs and 16 output ports, each M bits, of corresponding address values and all ports functioning in parallel and RANDOM(at a time I might only use few ports out of 16 with random port accessing). Do you guys think this is even possible to have a ROM structure like this? Family: Vertex-6.

Sample examples are appreciated.

Thanks!

 

[achaleus]

Then it will become a distributed ROM rather than block ROM, if you want to use only block rom try using single butterfly repeatedly until you compute that particular stage butterflies,

I doubt, how you computing inplace computation(general architecture). From where you are reading time domain data and where you are storing those values again.

 

[SharpWeapon]

Thanks for the reply achaleus. Well, it is possible to reuse one butterfly but very inefficient and slow, I am using Piplined butterflies.

Time domain data will stream from an antenna through ADC.

 

[ads-ee]

With block RAM you can build a true dual port ROM which means you'll have two read ports. To have an N-port ROM you'll end up either a) having multiple block rams (N/2) to implement the N-port ROM or b) an N-port distributed ROM. In either case you will be using more resources than a single block memory.

Regards

 

[SharpWeapon]

Thanks ads-ee. I can think of using N-port distributed ROM as faster and more efficient (resource wise) than having N/2 block RAMs. What are the other differences of both solutions tho? And where does that N/2 comes from?

 

[TrickyDicky]

Distrubted rom will use a lot of resources, and have worse timing performance than a BRAM.

 

[ads-ee]

N/2 as you can implement the block RAM as a dual port (2 read port) ROM, assuming the contents of the dual port ROM are the same.

The differences? One is using block memory (36Kb each) and the other is using distributed memory (32b each). So if there are a lot of small ROMs with shallow depth then it probably makes more sense to use distributed memory, or if you require deep memories then the block solution makes more sense.


regards

 

[SharpWeapon]

Hey TrickyDicky, thanks for the reply! Wont it be a waste of memory using one block for data size quite less than the total memory size, and imagine having N those blocks? Regarding the timing, at-least they should be proportional(assuming both are same size), otherwise how can reading from a big memory will be faster than reading from small LUTs?

ads-ee, thanks again man. I agree with the design selection.

Actually in my case, I have a total of ~66Kbits data to be divided into 6 memories, around 11Kbits on average in each. I think in this case I am option-less other than going for block RAMs. If I go for distributed I will end up having 300+ units for each of my 6 parts. A total fail. Don't you guys think?

 

[TrickyDicky]

if you dont use all the block ram, then yes, some will be wasted. But it will not affect timing. Designs will usually contain memories that are not 100% efficient, but thats the compromise you make. It depends what your design goal is.

 

[SharpWeapon]

Thanks TrickyDicky!