Hi shnain, your solution is ok, but my case is a bit different,can you solve it?....Like my design(FPGA) communicates with a CODEC which has a clk of 2MHz,but however the codec is a master here...You can't make any handshaking to that.Because it's clk is not controllable.....Is there any solution to sync this clk?....and sample the data with my synchronized FPGA clk?...
Clock domain synchronization is not a simple solution, because of the metastability problems. This problem is quite large and you should investigate a little on Internet to understand what it is. However, there is two solutions :
1 - for a single signal use 2 cascaded flip-flops, synchronized with the destination clock.
2 - for a dataflow, use a FIFO with two clock domains (the FIFO integrates the necessary logic to manage properly the clock domain crossing problems).