multiple clock divider

module clk_divider (
	clk_in,
	reset_n,
	clk_div8,
	clk_div16,
	clk_div32
);

input clk_in;
input reset_n;

output clk_div8;
output clk_div16;
output clk_div32;

//register output
//assign	clk_div8 = counter[2];
//assign	clk_div16 = counter[3];
//assign	clk_div32 = counter[4];

// only for xilinx
BUFG	BUFG_U0 ( .I(counter[2], .O(clk_div8));
BUFG	BUFG_U1 ( .I(counter[3], .O(clk_div16));
BUFG	BUFG_U2 ( .I(counter[4], .O(clk_div32));

reg	[4:0] counter;

always @(posedge clk_in or negedge reset_n)
	if (!reset_n)
		counter <= 5'b00000;
	else
		counter <= counter + 1;
		
endmodule

-------------------------------------------------------------------------------
-- KeyShore
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity clk_gen is
  port (
    system_reset : in  std_logic;       --  reset
    clk_in       : in  std_logic;       --  clk in
    clk_div8     : out std_logic;
    clk_div16    : out std_logic;
    clk_div32    : out std_logic

    );
end clk_gen;

architecture clk_gen_a of clk_gen is
  signal count1 : std_logic_vector(4 downto 0);
begin  -- clk_gen_a of clk_gen
  process(clk_in, system_reset)  -- proc to gen  clk_div8 counter
  begin
    if system_reset = '0' then
      count1 <= (others => '0');
    elsif rising_edge(clk_in) then
      count1 <= count1 +1;
    end if;
  end process;

  clk_div8  <= count1(2);
  clk_div16 <= count1(3);
  clk_div32 <= count1(4);

end clk_gen_a;