# multiple clock divider

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#### triump.ar

##### Junior Member level 2 hi,
i have to design a clock divider ckt which will divide the input clock of 64 mhz by multiple clock
1 is divide by 8 then second divide by 16 then divide by 32...
how to do it in a single program...

#### cherjier

##### Member level 5 if you are using an FPGA, and DCM/PLL will do the clock dividing.

if you just wan the clock to be divided, the most direct method is using a counter.
i have write you a simple code for the divider..

Code:
module clk_divider (
clk_in,
reset_n,
clk_div8,
clk_div16,
clk_div32
);

input clk_in;
input reset_n;

output clk_div8;
output clk_div16;
output clk_div32;

//register output
//assign	clk_div8 = counter;
//assign	clk_div16 = counter;
//assign	clk_div32 = counter;

// only for xilinx
BUFG	BUFG_U0 ( .I(counter, .O(clk_div8));
BUFG	BUFG_U1 ( .I(counter, .O(clk_div16));
BUFG	BUFG_U2 ( .I(counter, .O(clk_div32));

reg	[4:0] counter;

always @(posedge clk_in or negedge reset_n)
if (!reset_n)
counter <= 5'b00000;
else
counter <= counter + 1;

endmodule

#### triump.ar

##### Junior Member level 2 hey, i want to do it in vhdl...

#### cherjier

##### Member level 5 than u just rewrite the code in vhdl..that's all
the architecture are the same...

used a 5bits counter from 00000 to 11111 than repeat... u will get all the div value that you wan. bit 2 is div 8, bit3 is div16 and bit4 is div32 and you are done

### triump.ar

Points: 2

#### kvingle

##### Full Member level 5 Code:
-------------------------------------------------------------------------------
-- KeyShore
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity clk_gen is
port (
system_reset : in  std_logic;       --  reset
clk_in       : in  std_logic;       --  clk in
clk_div8     : out std_logic;
clk_div16    : out std_logic;
clk_div32    : out std_logic

);
end clk_gen;

architecture clk_gen_a of clk_gen is
signal count1 : std_logic_vector(4 downto 0);
begin  -- clk_gen_a of clk_gen
process(clk_in, system_reset)  -- proc to gen  clk_div8 counter
begin
if system_reset = '0' then
count1 <= (others => '0');
elsif rising_edge(clk_in) then
count1 <= count1 +1;
end if;
end process;

clk_div8  <= count1(2);
clk_div16 <= count1(3);
clk_div32 <= count1(4);

end clk_gen_a;

use bufg primitives for outputs if you are using a xilinx device.

#### triump.ar

##### Junior Member level 2 thanx..i got the point

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