In my case, I wanted some parts of my design to be really fast and to save as much clock cycle as possible. Lets say I have a Core with 10 inputs. This core carries out some calculations on these 10 inputs. So instead of reading the 10 inputs in 10 different clock cycles (one clock cycle for each input to be read form the BRAM), I implemented 10 different Brams and I read the 10 Inputs from the 10 different BRAMs in one clock cycle (saving 9 clock cycles).
I dun actually get the question, however the write width is the number of bits you write in one clock cycle to one memory location (one memory location size in bits) the write depth is the size of the whole memory you are implementing
lets assume you want to save 1KB of data in memory organized as 1 byte at a time (based on ur application..might be 2 bytes in one memory location):
case: 1KB of data and 1 Byte at a time
write width: 1 Byte = 8 bits..so you write 8 in the Write Width box
write depth: 1K = 1024 location..so you write 1024 in the Write Depth box
case: 1KB of data and 2 Bytes at a time
write width: 2 Bytes = 16 bits..so you write 16 in the Write Width box
write depth: 1K = 1024 location..but each location has 2 bytes..so you need 1024/2 = 512 locations..so you write 512 in the write depth box
so again I believe its all based on what do you want to implement and how do you want to access it.
One more time, please note that am not that expert..am just sharing with you what I do understand so far..some information might be wrong, but for me its working
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https://www.xilinx.com/support/documentation/user_guides/ug190.pdf
this might be helpfull as well..check chapter 4