Hi,
Apologize for not proving details at the first time.
My design, chip-top, containing 2 major sub-module, A & B.
Whole chip is in 5V power domain always on except module A is in 1.5V and
It can be shutdown for saving power.
Foundry provides two sets of Std. cell:
1.5V base.
5V base, level-shifter with isolation.
Method 1: synthesis whole chip top-down
read_rtl
load_upf
current_design chip_top
Compile_ultra
Above did not pass timing, lots of violation.
Method 2: synthesis 1.5V module A first then do the whole chip
read_rtl
load_upf
current_design A
compile_ultra // synthesis sub-module A
current_design chip_top
set_dont_touch A
compile_ultra // synthesis whole chip
no violation, timing pass
Can anyone advice what I was missing in Method 1(top-down)? Any inputs will be appreciated.