q1: Do place and route tools synthesize multi-port register files with "write-first" read-during-write behaviour or are they restricted to only "undefined" read-during-write?
q2: In a super-scalar cpu would the multi-ported register files be synthesised ok by place-and-route tools or a specialised compiler is usually used?
Here's a regfile that implies read during write = "old value"; please note that I'm rusty on 2D arrays/memories so this may not be syntactically perfect.
Code:
module regfile( input clk,
input reset,
input [3:0] read_addr,
output [7:0] read_data,
input [3:0] write_addr,
input write_valid,
input [7:0] write_data );
reg [7:0] memory[0:15];
always @(posedge clk)
begin
if( reset )
begin
read_data <= 8'hxx; // don't care
end
else
begin
if( read_valid )
begin
read_data <= memory[read_addr];
end
if( write_valid )
begin
memory[write_addr] <= write_data;
end
end
end
endmodule
And here's read during write behavior being "new value"; the only change is an additional conditional in the if( read_valid ) block: