Multi-Port RAM - how many ports do exist?

[ivlsi]

Hi All,

As for the Multi-Port RAM, how many ports might be implemented?

Actually I need to store an array of data, which could be accessed from 5 different sources while each source can access the array with both read and write accesses.

Could the array be implemented with 5-Ports full-duplex RAM (I even don't know whether exists such one) or it should be implemented with flops?

How many Ports RAM can provide nowadays ASIC vendors?

Thank you!

 

[rca]

At least two port is usual.
One question, what is your array size?
Perhap it is more easy to implement this with flops, if you code properly the flop could be the simple, I mean without reset and enable pin. Only ck, d, sd, se and q pins are needed.

 

[ivlsi]

Actually I need to implement the following arrays:
15x256 <- four such arrays, 4 sources may access the array simultaneously (no arbitration, a single clock access)
256x256 <- four such arrays, 4 sources may access the array simultaneously (no arbitration, a single clock access)

So, flip flops or multi-port memories?

If I'm comparing a single FF without reset and enable and a regular SRAM cell, how much the flip flop will be bigger? Who consume more current? How to choose what to use?

 

[rca]

that's depends:
1- IP exist or not and silicon proven?
2- the architecture: for one project, I used flop instead memories for 18*264, 264=11 words of 24bits access indenpendently, I implemented that, because I have enough area, I did not want to add a test mode & BIST logic for the added memory, and the power consumption was similar.

Are you able to have a clock 4 time faster on the memories instead the design to have "a full access" for all yours sources?

 

[ivlsi]

Are you able to have a clock 4 time faster on the memories instead the design to have "a full access" for all yours sources?

Unfortunately no...

Could you please give some area estimation for flip flops without reset and enable and a static RAM cell? What's the ration?